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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8569185 B1

PDFFull Text
Expired
Date of Patent:
Oct. 29, 2013

Filed:

Feb. 05, 2010

Method of fabricating gate electrode using a treated hard mask

Applicants:

Matt Yeh, Hsinchu, TW;

Hui Ouyang, Chuebi, TW;

Han-pin Chung, Fongshan, TW;

Shiang-bau Wang, Pingzchen, TW;

Inventors:

Matt Yeh, Hsinchu, TW;

Hui Ouyang, Chuebi, TW;

Han-Pin Chung, Fongshan, TW;

Shiang-Bau Wang, Pingzchen, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Attorney:

Haynes and Boone, LLP

Primary Examiner:

Calvin Choi

Int. Cl.
CPC ...
H01L 21/31 (2006.01); H01L 21/469 (2006.01); H01L 21/8238 (2006.01); H01L 21/425 (2006.01); H01L 21/3205 (2006.01); H01L 21/4763 (2006.01); H01L 21/44 (2006.01); H01L 21/027 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for fabricating an integrated device is disclosed. In an embodiment, a hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided to the hard mask layer to make the hard mask layer more resistant to a wet etch solution. Then, a patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure.

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Quick Actions:

Yeh, Matt. (2013). Method of fabricating gate electrode using a treated hard mask (U.S. Patent No. 8569185). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8569185

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