The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2013

Filed:

Mar. 15, 2012
Applicants:

Richard M. Barth, Palo Alto, CA (US);

Frederick A. Ware, Los Altos Hills, CA (US);

Donald C. Stark, Los Altos, CA (US);

Craig E. Hampel, San Jose, CA (US);

Paul G. Davis, San Jose, CA (US);

Abhijit M. Abhyankar, Sunnyvale, CA (US);

James A. Gasborro, Mountain View, CA (US);

David Nguyen, San Jose, CA (US);

Inventors:

Richard M. Barth, Palo Alto, CA (US);

Frederick A. Ware, Los Altos Hills, CA (US);

Donald C. Stark, Los Altos, CA (US);

Craig E. Hampel, San Jose, CA (US);

Paul G. Davis, San Jose, CA (US);

Abhijit M. Abhyankar, Sunnyvale, CA (US);

James A. Gasborro, Mountain View, CA (US);

David Nguyen, San Jose, CA (US);

Assignee:

Rambus Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit, over a first plurality of wires, to the DRAM a first code to indicate that first data is to be written to the DRAM and a column address to indicate a column location of a memory core in the DRAM where the first data is to be written. The interface is further to transmit a second code to indicate whether mask information for the first data will be sent to the DRAM. If the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent after the second code is sent. The interface is further to transmit to the DRAM, over a second plurality of wires separate from the first plurality of wires, the first data.


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