The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2013
Filed:
Sep. 05, 2012
Paul S. Andry, Yorktown Heights, NY (US);
Russell A. Budd, Yorktown Heights, NY (US);
Bing Dang, Yorktown Heights, NY (US);
David Danovitch, Bromont, CA;
Benjamin V. Fasano, Yorktown Heights, NY (US);
Paul Fortier, Bromont, CA;
Luc Guerin, Bromont, CA;
Frank F. Libsch, Yorktown Heights, NY (US);
Sylvain Ouimet, Bromont, CA;
Chrirag S. Patel, Yorktown Heights, NY (US);
Paul S. Andry, Yorktown Heights, NY (US);
Russell A. Budd, Yorktown Heights, NY (US);
Bing Dang, Yorktown Heights, NY (US);
David Danovitch, Bromont, CA;
Benjamin V. Fasano, Yorktown Heights, NY (US);
Paul Fortier, Bromont, CA;
Luc Guerin, Bromont, CA;
Frank F. Libsch, Yorktown Heights, NY (US);
Sylvain Ouimet, Bromont, CA;
Chrirag S. Patel, Yorktown Heights, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.