The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2013
Filed:
Aug. 13, 2009
Jun Yang, Jiangsu, CN;
NA Bai, Jiangsu, CN;
Jie LI, Jiangsu, CN;
Chen HU, Jiangsu, CN;
Longxing Shi, Jiangsu, CN;
Jun Yang, Jiangsu, CN;
Na Bai, Jiangsu, CN;
Jie Li, Jiangsu, CN;
Chen Hu, Jiangsu, CN;
Longxing Shi, Jiangsu, CN;
Southeast University, , CN;
Abstract
A high-density and high-robustness sub-threshold memory cell circuit, having two PMOS transistors Pand Pand five NMOS transistors N˜N, wherein, the each base electrode of the two PMOS transistors and NMOS transistors N, N, and Nis connected with the local grid electrode respectively; the base electrode of the NMOS transistors Nand N, are grounded respectively; the NMOS transistor Nform an phase inverter with the PMOS transistor P, and the NMOS transistor Nform another phase inverter with the PMOS transistor P; the two phase inverters are connected with each other in a cross coupling manner via the cut-off NMOS transistor N, the output end of the phase inverter Nand Pdirectly connected to the input end of the phase inverter Nand P, and the output end of the phase inverter Nand Pconnected to the input end of the phase inverter Nand Pvia the cut-off NMOS transistor N; the NMOS transistor Nis connected with the write bit line (WBL) of the phase inverter Nand P, and the NMOS transistor Nis connected with the NOT WBL and read word line (RWL) of the phase inverter Nand P