The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2013

Filed:

Jan. 12, 2012
Applicants:

Xiaodong Yang, Hopewell Junction, NY (US);

Yanxiang Liu, Wappingers Falls, NY (US);

Vara Govindeswara Reddy Vakada, Beacon, NY (US);

Jinping Liu, Hopewell Junction, NY (US);

Min Dai, Mahwah, NJ (US);

Inventors:

Xiaodong Yang, Hopewell Junction, NY (US);

Yanxiang Liu, Wappingers Falls, NY (US);

Vara Govindeswara Reddy Vakada, Beacon, NY (US);

Jinping Liu, Hopewell Junction, NY (US);

Min Dai, Mahwah, NJ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner.


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