The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2013
Filed:
May. 23, 2011
Xiaoyan Liu, Beijing, CN;
Jiaqi Yang, Beijing, CN;
Jinfeng Kang, Beijing, CN;
Jingfeng Yang, Beijing, CN;
Bing Chen, Beijing, CN;
Xiaoyan Liu, Beijing, CN;
Jiaqi Yang, Beijing, CN;
Jinfeng Kang, Beijing, CN;
Jingfeng Yang, Beijing, CN;
Bing Chen, Beijing, CN;
Peking University, , CN;
Abstract
The invention provides a method of testing reliability of a semiconductor device, wherein the semiconductor device has negative bias temperature instability NBTI. The method comprises steps of: measuring a NBTI curve of a first set of semiconductor devices; measuring 1/f noise power spectrum density and drain current at a predetermined frequency for the first set of the semiconductor devices, under a condition that the first set of the semiconductor devices are biased at a gate electric field; measuring an equivalent oxide thickness EOT of gate dielectric of the first set of the semiconductor devices; measuring 1/f noise power spectrum density and drain current at the predetermined frequency for a second set of semiconductor devices, under a condition that the second set of the semiconductor devices are biased at the gate electric field; measuring an EOT of gate dielectric of the second set of the semiconductor devices; and evaluating a degradation characteristic of the second set of the semiconductor devices by using the NBTI curve of a first set of the semiconductor devices. The method saves the time required for testing the reliability of a large numbers of semiconductor devices, and will not cause damages to the second set of semiconductor devices.