The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2013

Filed:

May. 10, 2011
Applicants:

Robert W. Warren, Newport Beach, CA (US);

Nic Rossi, Causeway Bay, HK;

Inventors:

Robert W. Warren, Newport Beach, CA (US);

Nic Rossi, Causeway Bay, HK;

Assignee:

Conexant Systems, Inc., Irvine, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01);
U.S. Cl.
CPC ...
Abstract

Wafer level packaging (WLP) packages semiconductor dies onto a wafer structure. After the wafer level package is complete, individual packages are obtained by singulating the wafer level package. The resulting package has a small form factor suitable for miniaturization. Unfortunately conventional WLP have poor heat dissipation. An interposer with a thermal pad can be attached to the semiconductor die to facilitate improved heat dissipation. In one embodiment, the interposer can also provide a wafer substrate for the wafer level package. Furthermore, the interposer can be constructed using well established and inexpensive processes. The thermal pad attached to the interposer can be coupled to the ground plane of a system where heat drawn from the semiconductor die can be dissipated.


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