The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8552471 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 08, 2013

Filed:

Dec. 11, 2009
Applicants:

Yasuhiro Okamoto, Tokyo, JP;

Yuji Ando, Tokyo, JP;

Tatsuo Nakayama, Tokyo, JP;

Kazuki Ota, Tokyo, JP;

Takashi Inoue, Tokyo, JP;

Hironobu Miyamoto, Tokyo, JP;

Kazuomi Endo, Tokyo, JP;

Inventors:

Yasuhiro Okamoto, Tokyo, JP;

Yuji Ando, Tokyo, JP;

Tatsuo Nakayama, Tokyo, JP;

Kazuki Ota, Tokyo, JP;

Takashi Inoue, Tokyo, JP;

Hironobu Miyamoto, Tokyo, JP;

Kazuomi Endo, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
Abstract

There is provided a semiconductor apparatus capable of achieving both a reverse blocking characteristic and a low on-resistance. The semiconductor apparatus includes a first semiconductor layer including a channel layer, a source electrode formed on the first semiconductor layer, a drain electrode formed at a distance from the source electrode on the first semiconductor layer, and a gate electrode formed between the source electrode and the drain electrode on the first semiconductor layer. The drain electrode includes a first drain region where reverse current between the first semiconductor layer and the first drain region is blocked, and a second drain region formed at a greater distance from the gate electrode than the first drain region, where a resistance between the first semiconductor layer and the second drain region is lower than a resistance between the first semiconductor layer and the first drain region.


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