The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 01, 2013
Filed:
Jun. 01, 2011
George Samachisa, San Jose, CA (US);
Luca Fasoli, Campbell, CA (US);
Masaaki Higashitani, Cupertino, CA (US);
Roy Edwin Scheuerlein, Cupertino, CA (US);
George Samachisa, San Jose, CA (US);
Luca Fasoli, Campbell, CA (US);
Masaaki Higashitani, Cupertino, CA (US);
Roy Edwin Scheuerlein, Cupertino, CA (US);
Sandisk 3D LLC, Milpitas, CA (US);
Abstract
A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.