The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 01, 2013
Filed:
Aug. 30, 2010
Jung Hyun Park, Gyunggi-do, KR;
Nam Keun OH, Daejeon, KR;
Sang Duck Kim, Chungcheongbuk-do, KR;
Jong Gyu Choi, Chungcheongnam-do, KR;
Young Ji Kim, Daejeon, KR;
Ji Eun Kim, Gyunggi-do, KR;
Myung Sam Kang, Gyunggi-do, KR;
Jung Hyun Park, Gyunggi-do, KR;
Nam Keun Oh, Daejeon, KR;
Sang Duck Kim, Chungcheongbuk-do, KR;
Jong Gyu Choi, Chungcheongnam-do, KR;
Young Ji Kim, Daejeon, KR;
Ji Eun Kim, Gyunggi-do, KR;
Myung Sam Kang, Gyunggi-do, KR;
Samsung Electro-Mechanics Co., Ltd., Suwon, KR;
Abstract
Provided is a ball grid array substrate, a semiconductor chip package, and a method of manufacturing the same. The ball grid array substrate includes an insulating layer having a first surface providing a mounting region for a semiconductor chip, a second surface opposing the first surface, and an opening connecting the second surface with the mounting region of the semiconductor chip, and a circuit pattern buried in the second surface. Since the ball grid array substrate is manufactured by a method of stacking two insulating layers, existing devices can be used, and the ball grid array substrate can be manufactured as an ultra thin plate. In addition, since the circuit pattern is buried in the insulating layer, a high-density circuit pattern can be formed.