The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8546936 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 01, 2013

Filed:

Jun. 18, 2010
Applicants:

Pakhorudin Hussin, Kedah, MY;

Murugasan Manikam Achari, Penang, MY;

Tee-eu Jin, Penang, MY;

Kwet Nam Wong, Penang, MY;

Inventors:

Pakhorudin Hussin, Kedah, MY;

Murugasan Manikam Achari, Penang, MY;

Tee-Eu Jin, Penang, MY;

Kwet Nam Wong, Penang, MY;

Assignee:

Spansion LLC, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/10 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A substrate surface of a semiconductor package, comprising: a plurality of product forming areas to provide mounting spaces of semiconductor chips. The substrate surface also comprises a plurality of staggered offset mesh block areas surrounding the plurality of product forming areas. The plurality of staggered offset mesh block areas minimize mold bleeding from a mold cavity of the semiconductor package to outer areas of the substrate surface.


Find Patent Forward Citations

Hussin, Pakhorudin. (2013). Method and structure of minimizing mold bleeding on a substrate surface of a semiconductor package (U.S. Patent No. 8546936). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8546936

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