The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2013

Filed:

Jun. 23, 2011
Applicants:

Deok-young Jung, Seoul, KR;

Gil-heyun Choi, Seoul, KR;

Suk-chul Bang, Yongin-si, KR;

Byung-lyul Park, Seoul, KR;

Kwang-jin Moon, Suwon-si, KR;

Dong-chan Lim, Suwon-si, KR;

Inventors:

Deok-young Jung, Seoul, KR;

Gil-heyun Choi, Seoul, KR;

Suk-chul Bang, Yongin-si, KR;

Byung-lyul Park, Seoul, KR;

Kwang-jin Moon, Suwon-si, KR;

Dong-chan Lim, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/283 (2006.01);
U.S. Cl.
CPC ...
Abstract

The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern.


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