The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 2013
Filed:
May. 31, 2012
Jeanne P. Bickford, Essex Junction, VT (US);
Eric A. Foreman, Fairfax, VT (US);
Mark W. Kuemerle, Essex Junction, VT (US);
Susan K. Lichtensteiger, Essex Junction, VT (US);
Jeanne P. Bickford, Essex Junction, VT (US);
Eric A. Foreman, Fairfax, VT (US);
Mark W. Kuemerle, Essex Junction, VT (US);
Susan K. Lichtensteiger, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of optimizing power and timing for an integrated circuit (IC) chip, which uses an IC technology that exhibits temperature inversion, by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges. A high voltage is selected that meets a closed timing analysis across a full temperature range to meet a timing performance and a low voltage is selected to meet the timing performance and the power performance across a lower temperature range to a temperature cut point in the higher temperature range. The IC chip is turned on at the high voltage and the high voltage is lowered to the low voltage when the temperature cut point is exceeded to meet the power performance while maintaining the timing performance.