The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 2013
Filed:
Dec. 02, 2010
Eric C. Cota-robles, Portland, OR (US);
Andy Glew, Hillsboro, OR (US);
Stalinselvaraj Jeyasingh, Beaverton, OR (US);
Alain Kagi, Portland, OR (US);
Michael A. Kozuch, Export, PA (US);
Gilbert Neiger, Portland, OR (US);
Richard Uhlig, Hillsboro, OR (US);
Eric C. Cota-Robles, Portland, OR (US);
Andy Glew, Hillsboro, OR (US);
Stalinselvaraj Jeyasingh, Beaverton, OR (US);
Alain Kagi, Portland, OR (US);
Michael A. Kozuch, Export, PA (US);
Gilbert Neiger, Portland, OR (US);
Richard Uhlig, Hillsboro, OR (US);
Intel Corporation, Santa Clara, unknown;
Abstract
One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine. The invalidation operation belongs to a non-empty set of invalidation operations composed of a union of () a possibly empty set of operations that invalidate a variable number of TLB entries, () a possibly empty set of operations that invalidate exactly one TLB entry, () a possibly empty set of operations that invalidate the plurality of TLB entries, () a possibly empty set of operations that enable and disable use of virtual memory, and () a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries.