The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 2013
Filed:
Feb. 28, 2012
Ryan T. Hirose, Colorado Springs, CO (US);
Fredrick Jenne, Sunnyvale, CA (US);
Vijay Srinivasaraghavan, Colorado Springs, CO (US);
Igor G. Kouznetsov, San Jose, CA (US);
Paul Fredrick Ruths, Woodland Park, CO (US);
Cristinel Zonte, Colorado Springs, CO (US);
Bogdan Georgescu, Colorado Springs, CO (US);
Leonard Vasile Gitlan, Colorado Springs, CO (US);
James Paul Myers, Woodinville, WA (US);
Ryan T. Hirose, Colorado Springs, CO (US);
Fredrick Jenne, Sunnyvale, CA (US);
Vijay Srinivasaraghavan, Colorado Springs, CO (US);
Igor G. Kouznetsov, San Jose, CA (US);
Paul Fredrick Ruths, Woodland Park, CO (US);
Cristinel Zonte, Colorado Springs, CO (US);
Bogdan Georgescu, Colorado Springs, CO (US);
Leonard Vasile Gitlan, Colorado Springs, CO (US);
James Paul Myers, Woodinville, WA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell.