Replacement gate process flow for highly scaled semiconductor devices

Abstract

A method disclosed herein includes forming sacrificial gate structures for a PFET and NFET transistor, removing the sacrificial gate structures and forming a replacement P-type gate structure for the PFET transistor and a replacement N-type gate structure for the NFET transistor, forming P-contact openings and N-contact openings in at least one layer of insulating material, wherein the P-contact openings expose portions of a P-active region and the N-contact openings expose portions of an N-active region, forming a masking layer that covers the exposed portions of the N-active region, performing an etching process though the P-contact openings in the layer of insulating material to define source/drain cavities in the P-active region proximate the replacement gate structure of the PFET transistor, and performing an epitaxial deposition process through the P-contact openings to form source/drain regions comprised of a semiconducting material in at least the source/drain cavities of the PFET transistor.