The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2013

Filed:

Oct. 16, 2012
Applicants:

Imec, Leuven, BE;

Samsung Electronics Co., Ltd., Suwon-si, KR;

Taiwan Semiconductor Manufacturing Company, Ltd., HsinChu, TW;

Inventors:

Hag-Ju Cho, Seoul, KR;

Anabela Veloso, Leuven, BE;

HongYu Yu, Singapore, SG;

Stefan Kubicek, Pellenberg, BE;

Shou-Zen Chang, Hsinchu Country, TW;

Assignees:

IMEC, Leuven, BE;

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.


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