The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2013

Filed:

Apr. 26, 2011
Applicants:

William French, San Jose, CA (US);

Vladislav Vashchenko, Palo Alto, CA (US);

Richard Wendell Foote, Jr., Burleson, TX (US);

Alexei Sadovnikov, Sunnyvale, CA (US);

Punit Bhola, South Portland, ME (US);

Peter J. Hopper, San Jose, CA (US);

Inventors:

William French, San Jose, CA (US);

Vladislav Vashchenko, Palo Alto, CA (US);

Richard Wendell Foote, Jr., Burleson, TX (US);

Alexei Sadovnikov, Sunnyvale, CA (US);

Punit Bhola, South Portland, ME (US);

Peter J. Hopper, San Jose, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
Abstract

A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor.


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