The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 2013
Filed:
Aug. 31, 2011
Laung-terng Wang, Sunnyvale, CA (US);
Nur A. Touba, Austin, TX (US);
Michael S. Hsiao, Blacksburg, VA (US);
Zhigang Jiang, Burlingame, CA (US);
Shianling Wu, Princeton Junction, NJ (US);
Laung-Terng Wang, Sunnyvale, CA (US);
Nur A. Touba, Austin, TX (US);
Michael S. Hsiao, Blacksburg, VA (US);
Zhigang Jiang, Burlingame, CA (US);
Shianling Wu, Princeton Junction, NJ (US);
Syntest Technologies, Inc., Sunnyvale, CA (US);
Abstract
A method and apparatus for testing a scan-based 3D integrated circuit (3DIC) using time-division demultiplexing/multiplexing allowing for high-data-rate scan patterns applied at input/output pads converting into low-data-rate scan patterns applied to each embeddded module in the 3DIC. A set of 3D design guidelines is proposed to reduce the number of test times and the number of through-silicon vias (TSVs) required for both pre-bond testing and post-bond testing. The technique allows reuse of scan patterns developed for pre-bond testing of each die (layer) for post-bond testing of the whole 3DIC. It further reduces test application time without concerns for I/O pad count limit and risks for fault coverage loss.