The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 2013
Filed:
Aug. 16, 2012
Sheng-tsai Wu, Taoyuan County, TW;
John H. Lau, Taipei, TW;
Heng-chieh Chien, New Taipei, TW;
Ra-min Tain, New Taipei, TW;
Ming-ji Dai, Hsinchu, TW;
Yu-lin Chao, Hsinchu, TW;
Sheng-Tsai Wu, Taoyuan County, TW;
John H. Lau, Taipei, TW;
Heng-Chieh Chien, New Taipei, TW;
Ra-Min Tain, New Taipei, TW;
Ming-Ji Dai, Hsinchu, TW;
Yu-Lin Chao, Hsinchu, TW;
Industrial Technology Research Institute, Hsinchu, TW;
Abstract
A chip stacking structure including a carrier, a first redistribution layer, a second redistribution layer, at least one first chip, at least one second chip, and at least one conductor is provided. The carrier has a first surface and a second surface opposite to each other. The carrier has at least one through hole. The first and second redistribution layers are disposed on the first and second surfaces of the carrier, respectively. The first and second chips are disposed on the first and second surfaces of the carrier and electrically connected with the first and second redistribution layers, respectively. The conductor is disposed on one of the first and second chips. The conductor is disposed in the through hole. The first and second chips are electrically connected by the conductor. A gap is formed between the conductor and an inner wall of the carrier which surrounds the through hole.