The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 2013
Filed:
Sep. 10, 2010
Annie Lum, San Jose, CA (US);
Derek C. Tao, Fremont, CA (US);
Cheng Hung Lee, Hsinchu, TW;
Chung-ji LU, Fongyuan, TW;
Hong-chen Cheng, Hsinchu, TW;
Vineet Kumar Agrawal, Santa Clara, CA (US);
Keun-young Kim, Campbell, CA (US);
Pyong Yun Cho, Fremont, CA (US);
Annie Lum, San Jose, CA (US);
Derek C. Tao, Fremont, CA (US);
Cheng Hung Lee, Hsinchu, TW;
Chung-Ji Lu, Fongyuan, TW;
Hong-Chen Cheng, Hsinchu, TW;
Vineet Kumar Agrawal, Santa Clara, CA (US);
Keun-Young Kim, Campbell, CA (US);
Pyong Yun Cho, Fremont, CA (US);
Abstract
The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas.