The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8503259 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 06, 2013

Filed:

Mar. 17, 2009
Applicants:

Shogo Shibazaki, Kawasaki, JP;

Shinkichi Gama, Kawasaki, JP;

Hideyuki Negi, Kawasaki, JP;

Takeshi Nagase, Kawasaki, JP;

Chikahiro Deguchi, Kawasaki, JP;

Yutaka Sekino, Kawasaki, JP;

Inventors:

Shogo Shibazaki, Kawasaki, JP;

Shinkichi Gama, Kawasaki, JP;

Hideyuki Negi, Kawasaki, JP;

Takeshi Nagase, Kawasaki, JP;

Chikahiro Deguchi, Kawasaki, JP;

Yutaka Sekino, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1≦k≦n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data.


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Shibazaki, Shogo. (2013). Memory test method and memory test device (U.S. Patent No. 8503259). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8503259

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