The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 30, 2013
Filed:
Apr. 30, 2012
Kwang-jin Moon, Suwon-si, KR;
Byung-lyul Park, Seoul, KR;
Do-sun Lee, Gwangju, KR;
Gil-heyun Choi, Seoul, KR;
Suk-chul Bang, Yongin-si, KR;
Dong-chan Lim, Suwon-si, KR;
Deok-young Jung, Seoul, KR;
Kwang-Jin Moon, Suwon-si, KR;
Byung-Lyul Park, Seoul, KR;
Do-Sun Lee, Gwangju, KR;
Gil-Heyun Choi, Seoul, KR;
Suk-Chul Bang, Yongin-si, KR;
Dong-Chan Lim, Suwon-si, KR;
Deok-Young Jung, Seoul, KR;
Samsung Electronics Co., Ltd., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;
Abstract
In a method of manufacturing a semiconductor device, a front end of line (FEOL) process may be performed on a semiconductor substrate to form a semiconductor structure. A back end of line (BEOL) process may be performed on the semiconductor substrate to form a wiring structure electrically connected to the semiconductor structure, thereby formed a semiconductor chip. A hole may be formed through a part of the semiconductor chip. A preliminary plug may have a dimple in the hole. The preliminary plug may be expanded into the dimple by a thermal treatment process to form a plug. Thus, the plug may not have a protrusion protruding from the upper surface of the semiconductor chip, so that the plug may be formed by the single CMP process.