The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 2013
Filed:
Aug. 10, 2012
Mukta G. Farooq, Hopewell Junction, NY (US);
Robert Hannon, Wappingers Falls, NY (US);
Subramanian S. Iyer, Mount Kisco, NY (US);
Steven J. Koester, Ossining, NY (US);
Fei Liu, Mount Kisco, NY (US);
Sampath Purushothaman, Yorktown Heights, NY (US);
Albert M. Young, Fishkill, NY (US);
Roy R. Yu, Poughkeepsie, NY (US);
Mukta G. Farooq, Hopewell Junction, NY (US);
Robert Hannon, Wappingers Falls, NY (US);
Subramanian S. Iyer, Mount Kisco, NY (US);
Steven J. Koester, Ossining, NY (US);
Fei Liu, Mount Kisco, NY (US);
Sampath Purushothaman, Yorktown Heights, NY (US);
Albert M. Young, Fishkill, NY (US);
Roy R. Yu, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A 3D integrated circuit structure is provided. The 3D integrated circuit structure includes an interface wafer including a first wiring layer, a first active circuitry layer including active circuitry, and a wafer including active circuitry. The first active circuitry layer is bonded face down to the interface wafer, and the wafer is bonded face down to the first active circuitry layer. The first active circuitry layer is lower-cost than the wafer.