The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2013

Filed:

Dec. 22, 2010
Applicants:

Rohith Sood, Portland, OR (US);

Zheng Chen, Upper Macungie, PA (US);

Loren Mclaury, Hillsboro, OR (US);

Inventors:

Rohith Sood, Portland, OR (US);

Zheng Chen, Upper Macungie, PA (US);

Loren McLaury, Hillsboro, OR (US);

Assignee:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Techniques are provided which may be used to reduce power consumed by memory circuits. In one example, a programmable logic device (PLD) includes a plurality of static random access memory (SRAM) cells adapted to configure the PLD for an intended use. A pair of bitlines are connected to the SRAM cells. At least one of the SRAM cells is adapted to provide data signals to the bitlines in response to a wordline signal received by the one of the SRAM cells during a read operation. A sense amplifier is connected to the bitlines and adapted to detect a data value from the data signals in response to a trigger signal received by the sense amplifier during the read operation. Logic is adapted to delay the trigger signal relative to the wordline signal to permit the data signals to settle before the sense amplifier detects the data value.


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