The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 2013
Filed:
Jun. 11, 2010
You-jen Wang, Taipei, TW;
Shen-iuan Liu, Taipei, TW;
Feng Wei Kuo, Zhudong Township, Hsinchu County, TW;
Chewn-pu Jou, Hsinchu, TW;
Fu-lung Hsueh, Cranbury, NJ (US);
You-Jen Wang, Taipei, TW;
Shen-Iuan Liu, Taipei, TW;
Feng Wei Kuo, Zhudong Township, Hsinchu County, TW;
Chewn-Pu Jou, Hsinchu, TW;
Fu-Lung Hsueh, Cranbury, NJ (US);
Taiwan Semiconductor Manufacturing Co., Ltd, Hsin-Chu, TW;
National Taiwan University, Taipei, TW;
Abstract
A time amplifier circuit has first and second inverters and first and second pull-down paths. Each inverter includes a first NMOS transistor and a first PMOS transistor. A source of the first NMOS transistor is coupled to a ground node directly or through a first additional NMOS transistor having a gate coupled to a respective input node. The first and second inverters are coupled to first and second input nodes and to first and second output nodes, respectively. The first pull-down path is from the first output node to the ground node and is enabled in response to the first input signal and the second output signal being high. The second pull-down path is from the second output node to ground and is enabled in response to the second input signal and the first output signal being high.