The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 2013
Filed:
Jul. 23, 2012
Harry Barowski, Boeblingen, DE;
Thomas Brunschwiler, Thalwil, CH;
Hubert Harrer, Schoenaich, DE;
Andreas Huber, Leonberg, DE;
Bruno Michel, Zurich, CH;
Tim Niggemeier, Laatzen, DE;
Stephan Paredes, Zurich, CH;
Jochen Supper, Herrenberg, DE;
Harry Barowski, Boeblingen, DE;
Thomas Brunschwiler, Thalwil, CH;
Hubert Harrer, Schoenaich, DE;
Andreas Huber, Leonberg, DE;
Bruno Michel, Zurich, CH;
Tim Niggemeier, Laatzen, DE;
Stephan Paredes, Zurich, CH;
Jochen Supper, Herrenberg, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.