The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 2013
Filed:
Aug. 04, 2011
Jasmin Ajanovic, Portland, OR (US);
Mahesh Wagh, Portland, OR (US);
Prashant Sethi, Folsom, CA (US);
Debendra Das Sharma, Santa Clara, CA (US);
David Harriman, Portland, OR (US);
Mark Rosenbluth, Uxbridge, MA (US);
Ajay Bhatt, Portland, OR (US);
Peter Barry, Ardnacrusha, IE;
Scott Dion Rodgers, Hillsboro, OR (US);
Anil Vasudevan, Portland, OR (US);
Sridhar Muthrasanallur, Puyallup, WA (US);
James Akiyama, Beaverton, OR (US);
Robert Blankenship, Tacoma, WA (US);
Ohad Falik, Kfar-Saba, IL;
Abraham Mendelson, Haifa, IL;
Ilan Pardo, Ramat-Hasharon, IL;
Eran Tamari, Ramat Gan, IL;
Eliezer Weissmann, Haifa, IL;
Doron Shamia, Modiin, IL;
Jasmin Ajanovic, Portland, OR (US);
Mahesh Wagh, Portland, OR (US);
Prashant Sethi, Folsom, CA (US);
Debendra Das Sharma, Santa Clara, CA (US);
David Harriman, Portland, OR (US);
Mark Rosenbluth, Uxbridge, MA (US);
Ajay Bhatt, Portland, OR (US);
Peter Barry, Ardnacrusha, IE;
Scott Dion Rodgers, Hillsboro, OR (US);
Anil Vasudevan, Portland, OR (US);
Sridhar Muthrasanallur, Puyallup, WA (US);
James Akiyama, Beaverton, OR (US);
Robert Blankenship, Tacoma, WA (US);
Ohad Falik, Kfar-Saba, IL;
Abraham Mendelson, Haifa, IL;
Ilan Pardo, Ramat-Hasharon, IL;
Eran Tamari, Ramat Gan, IL;
Eliezer Weissmann, Haifa, IL;
Doron Shamia, Modiin, IL;
Intel Corporation, Santa Clara, CA (US);
Abstract
A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.