The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 2013
Filed:
Jun. 11, 2009
Rajesh B. Khamankar, Coppell, TX (US);
Haowen Bu, Plano, TX (US);
Douglas Tad Grider, McKinney, TX (US);
Rajesh B. Khamankar, Coppell, TX (US);
Haowen Bu, Plano, TX (US);
Douglas Tad Grider, McKinney, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An integrated circuit containing a PMOS transistor with p-channel source/drain (PSD) regions which include a three layer PSD stack containing Si—Ge, carbon and boron. The first PSD layer is Si—Ge and includes carbon at a density between 5×10and 2×10atoms/cm. The second PSD layer is Si—Ge and includes carbon at a density between 5×10atoms/cmand 2×10atoms/cmand boron at a density above 5×10atoms/cm. The third PSD layer is silicon or Si—Ge, includes boron at a density above 5×10atoms/cmand is substantially free of carbon. After formation of the three layer epitaxial stack, the first PSD layer has a boron density less than 10 percent of the boron density in the second PSD layer. A process for forming an integrated circuit containing a PMOS transistor with a three layer PSD stack in PSD recesses.