The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2013

Filed:

Mar. 18, 2011
Applicants:

Peivand Tehrani, Campbell, CA (US);

LI Ding, San Jose, CA (US);

Narender Hanchate, San Jose, CA (US);

Rupesh Nayak, San Ramon, CA (US);

Yazdan Aghaghiri, Los Altos, CA (US);

Inventors:

Peivand Tehrani, Campbell, CA (US);

Li Ding, San Jose, CA (US);

Narender Hanchate, San Jose, CA (US);

Rupesh Nayak, San Ramon, CA (US);

Yazdan Aghaghiri, Los Altos, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and apparatus to provide a hierarchical timing model with crosstalk consideration is provided. In one embodiment, the method comprises performing block level analysis of a circuit, in one or a plurality of iterations, and storing per iteration data. The method further comprises, in one embodiment, utilizing the per iteration data in performing top level analysis of the circuit.


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