The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 18, 2013
Filed:
Oct. 08, 2010
Po-hung Chen, Taipei, TW;
Kuoyuan (Peter) Hsu, San Jose, CA (US);
David Yen, Chu-Bak, TW;
Sung-chieh Lin, Zhubei, TW;
Po-Hung Chen, Taipei, TW;
Kuoyuan (Peter) Hsu, San Jose, CA (US);
David Yen, Chu-Bak, TW;
Sung-Chieh Lin, Zhubei, TW;
Abstract
An input of a first inverter is configured to serve as an input node. An output of the first inverter is coupled to an input of a second inverter. An output of the second inverter is configured to serve as an output node. An input of a third inverter is coupled to an input of the first inverter. A gate of a first NMOS transistor is coupled to an output of the third inverter. A drain of the first NMOS transistor is coupled to the second inverter. A source of the first NMOS transistor is configured to serve as a level input node. When the input node is configured to receive a low logic level, the output node is configured to receive a voltage level provided by a voltage level at the level input node.