The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 18, 2013
Filed:
May. 21, 2010
Douglas B. Hershberger, Essex Junction, VT (US);
Richard A. Phelps, Colchester, VT (US);
Robert M. Rassel, Colchester, VT (US);
Stephen A. St. Onge, Colchester, VT (US);
Michael J. Zierak, Colchester, VT (US);
Douglas B. Hershberger, Essex Junction, VT (US);
Richard A. Phelps, Colchester, VT (US);
Robert M. Rassel, Colchester, VT (US);
Stephen A. St. Onge, Colchester, VT (US);
Michael J. Zierak, Colchester, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method. The JFET includes a bottom gate on an insulator layer, a channel region on the bottom gate and, on the channel region, source/drain regions and a top gate between the source/drain regions. STIs isolate the source/drain regions from the top gate and a DTI laterally surrounds the JFET to isolate it from other devices. Non-annular well(s) are positioned adjacent to the channel region and bottom gate (e.g., a well having the same conductivity type as the top and bottom gates can be connected to the top gate and can extend down to the insulator layer, forming a gate contact on only a portion of the channel region, and/or another well having the same conductivity type as the channel and source/drain regions can extend from the source region to the insulator layer, forming a source-to-channel strap).