The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8456946 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 04, 2013

Filed:

Dec. 22, 2010
Applicants:

Swaroop Ghosh, Hillsboro, OR (US);

Dinesh Somasekhar, Portland, OR (US);

Balaji Srinivasan, Hillsboro, OR (US);

Fatih Hamzaoglu, Portland, OR (US);

Inventors:

Swaroop Ghosh, Hillsboro, OR (US);

Dinesh Somasekhar, Portland, OR (US);

Balaji Srinivasan, Hillsboro, OR (US);

Fatih Hamzaoglu, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A NAND architecture for selecting a word line driver in a DRAM is disclosed. Separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.


Find Patent Forward Citations

Ghosh, Swaroop. (2013). Nand logic word line selection (U.S. Patent No. 8456946). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8456946

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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