The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2013

Filed:

Feb. 22, 2011
Applicants:

Shinnosuke Maeda, Nagoya, JP;

Takuya Torii, Komaki, JP;

Tetsuo Suzuki, Niwa-gun, JP;

Satoshi Hirano, Chita-gun, JP;

Inventors:

Shinnosuke Maeda, Nagoya, JP;

Takuya Torii, Komaki, JP;

Tetsuo Suzuki, Niwa-gun, JP;

Satoshi Hirano, Chita-gun, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01K 3/10 (2006.01); H05K 3/02 (2006.01); H05K 3/10 (2006.01); H05K 1/11 (2006.01);
U.S. Cl.
CPC ...
Abstract

A multilayer wiring substrate includes first principal surface side connection terminals arranged on a first principal surface of a stacked configuration; wherein, the first principal surface side connection terminals include an IC chip connection terminal, and a passive element connection terminal; the IC chip connection terminal is located in an opening formed in a resin insulating layer of an uppermost outer layer; the passive element connection terminal is formed of an upper terminal part formed on the resin insulating layer, and a lower terminal part located in an opening formed at a portion of an inner side of the upper terminal part in the resin insulating layer; and, wherein an upper face of the upper terminal part is higher than a reference surface, and an upper face of the IC chip connection terminal and the lower terminal part are identical in height to or lower in height than the reference surface.


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