The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2013

Filed:

Jul. 28, 2008
Applicants:

Rupert Krautbauer, Portland, OR (US);

Gerhard Huettl, Engelsberg, DE;

Andrej Lenz, Tittmoning, DE;

Erwin-peter Mayer, Burghausen, DE;

Rainer Winkler, Zorneding, DE;

Inventors:

Rupert Krautbauer, Portland, OR (US);

Gerhard Huettl, Engelsberg, DE;

Andrej Lenz, Tittmoning, DE;

Erwin-Peter Mayer, Burghausen, DE;

Rainer Winkler, Zorneding, DE;

Assignee:

Siltronic AG, Munich, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C30B 21/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor wafer is formed of a substrate wafer of single crystal silicon doped with dopant atoms of the n type or p type, with a front surface and a back surface, contains a layer deposited epitaxially on the front surface of the substrate wafer. The substrate wafer additionally includes an nor pdoped layer, which extends from the front surface of the substrate wafer into the substrate wafer and has a defined thickness. The semiconductor wafer is produced by a process in which dopant atoms of the n type or p type are introduced into the substrate wafer through the front surface of the substrate wafer, the dopant concentration in a layer which extends from the front surface of the substrate wafer into the substrate wafer being increased from the level nor pto the level nor p, and an epitaxial layer is then deposited on this layer.


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