The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2013

Filed:

Jan. 07, 2010
Applicants:

Dureseti Chidambarrao, Hopewell Junction, NY (US);

Sunfei Fang, Hopewell Junction, NY (US);

Yue Liang, Hopewell Junction, NY (US);

Xiaojun Yu, Hopewell Junction, NY (US);

Jun Yuan, Hopewell Junction, NY (US);

Inventors:

Dureseti Chidambarrao, Hopewell Junction, NY (US);

Sunfei Fang, Hopewell Junction, NY (US);

Yue Liang, Hopewell Junction, NY (US);

Xiaojun Yu, Hopewell Junction, NY (US);

Jun Yuan, Hopewell Junction, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor structure is provided that includes at least one asymmetric gate stack located on a surface of a semiconductor structure. The at least one asymmetric gate stack includes, from bottom to top, a high k gate dielectric, a sloped threshold voltage adjusting material layer and a gate conductor. A method of forming such a semiconductor structure is also provided in which a line of sight deposition process is used in forming the sloped threshold voltage adjusting material layer in which the deposition is tilted within respect to a horizontal surface of a semiconductor structure.


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