The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 2013
Filed:
Apr. 03, 2012
Sang Hoo Dhong, Hsin-Chu, TW;
Jiann-tyng Tzeng, Hsin-Chu, TW;
Kushare Mangesh Babaji, Maharashtra, IN;
Ramakrishnan Krishnan, Hsinchu, TW;
Lee-chung LU, Taipei, TW;
Ta-pen Guo, Cupertino, CA (US);
Sang Hoo Dhong, Hsin-Chu, TW;
Jiann-Tyng Tzeng, Hsin-Chu, TW;
Kushare Mangesh Babaji, Maharashtra, IN;
Ramakrishnan Krishnan, Hsinchu, TW;
Lee-Chung Lu, Taipei, TW;
Ta-Pen Guo, Cupertino, CA (US);
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A multi-operation mode application specific integrated circuit (ASIC) implemented in fully-depleted silicon-on-insulator (FDSOI) includes an ASIC implemented in FDSOI having a plurality of operating modes, plurality of power rails, and a power supply that provides voltages for the first and second rails corresponding to the plurality of operating modes. The power rails include at least one VDD rail, at least one Vss rail, a first rail for biasing a NGP region of PMOS transistor devices in the ASIC, and a second rail for biasing a PGP region of NMOS transistor devices in the ASIC.