The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2013
Filed:
Jan. 25, 2011
Yunjian (William) Jiang, San Jose, CA (US);
Arvind Srinivasan, San Jose, CA (US);
Joy Banerjee, District Burdwan, IN;
Yinghua LI, San Jose, CA (US);
Partha Das, Kolkata, IN;
Samit Chaudhuri, Cupertino, CA (US);
Yunjian (William) Jiang, San Jose, CA (US);
Arvind Srinivasan, San Jose, CA (US);
Joy Banerjee, District Burdwan, IN;
Yinghua Li, San Jose, CA (US);
Partha Das, Kolkata, IN;
Samit Chaudhuri, Cupertino, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.