The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2013

Filed:

Oct. 28, 2010
Applicants:

Harry Barowski, Boeblingen, DE;

Thomas Brunschwiler, Thalwil, CH;

Hubert Harrer, Schoenaich, DE;

Andreas Huber, Leonberg, DE;

Bruno Michel, Zurich, CH;

Tim Niggemeier, Laatzen, DE;

Stephan Paredes, Zurich, CH;

Jochen Supper, Herrenberg, DE;

Inventors:

Harry Barowski, Boeblingen, DE;

Thomas Brunschwiler, Thalwil, CH;

Hubert Harrer, Schoenaich, DE;

Andreas Huber, Leonberg, DE;

Bruno Michel, Zurich, CH;

Tim Niggemeier, Laatzen, DE;

Stephan Paredes, Zurich, CH;

Jochen Supper, Herrenberg, DE;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/20 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.


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