The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 2013
Filed:
Jun. 26, 2012
Kevin K. Chan, Staten Island, NY (US);
Abhishek Dube, Fishkill, NY (US);
Judson R. Holt, Wappingers Falls, NY (US);
Jinghong LI, Poughquag, NY (US);
Joseph S. Newbury, Irvington, NY (US);
Viorel Ontalus, Danbury, CT (US);
Dae-gyu Park, Poughquag, NY (US);
Zhengmao Zhu, Poughkeepsie, NY (US);
Kevin K. Chan, Staten Island, NY (US);
Abhishek Dube, Fishkill, NY (US);
Judson R. Holt, Wappingers Falls, NY (US);
Jinghong Li, Poughquag, NY (US);
Joseph S. Newbury, Irvington, NY (US);
Viorel Ontalus, Danbury, CT (US);
Dae-Gyu Park, Poughquag, NY (US);
Zhengmao Zhu, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Semiconductor structures are disclosed that include at least one FET gate stack located on a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. Embedded stressor elements are located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each stressor element includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material. At least one monolayer of dopant is located within the upper layer of each of the embedded stressor elements.