The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 2013
Filed:
Apr. 29, 2011
Emre Alptekin, Wappingers Falls, NY (US);
Dong-ick Lee, Fishkill, NY (US);
Viraj Yashawant Sardesai, Poughkeepsie, NY (US);
Cung DO Tran, Newburgh, NY (US);
Jian Yu, Danbury, CT (US);
Reinaldo Ariel Vega, Wappingers Falls, NY (US);
Rajasekhar Venigalla, Hopewell Junction, NY (US);
Emre Alptekin, Wappingers Falls, NY (US);
Dong-Ick Lee, Fishkill, NY (US);
Viraj Yashawant Sardesai, Poughkeepsie, NY (US);
Cung Do Tran, Newburgh, NY (US);
Jian Yu, Danbury, CT (US);
Reinaldo Ariel Vega, Wappingers Falls, NY (US);
Rajasekhar Venigalla, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.