The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 2013
Filed:
Mar. 11, 2010
James K. Schaeffer, Austin, TX (US);
Eric D. Luckowski, Round Rock, TX (US);
Todd C. Bailey, Poughkeepsie, NY (US);
Amy L. Child, Hopewell Junction, NY (US);
Daniel Jaeger, Wappingers Falls, NY (US);
Renee MO, Briarcliff Manor, NY (US);
Ying H. Tsang, Katy, TX (US);
James K. Schaeffer, Austin, TX (US);
Eric D. Luckowski, Round Rock, TX (US);
Todd C. Bailey, Poughkeepsie, NY (US);
Amy L. Child, Hopewell Junction, NY (US);
Daniel Jaeger, Wappingers Falls, NY (US);
Renee Mo, Briarcliff Manor, NY (US);
Ying H. Tsang, Katy, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method and apparatus are described for fabricating metal gate electrodes () over a high-k gate dielectric layer () having a rare earth oxide capping layer () in at least the NMOS device area by treating the surface of a rare earth oxide capping layer () with an oxygen-free plasma process () to improve photoresist adhesion, forming a patterned photoresist layer () directly on the rare earth oxide capping layer (), and then applying a wet etch process () to remove the exposed portion of the rare earth oxide capping layer () from the PMOS device area.