The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 26, 2013
Filed:
Oct. 28, 2010
Harry Barowski, Boeblingen, DE;
Thomas Brunschwiler, Thalwil, CH;
Hubert Harrer, Schoenaich, DE;
Andreas Huber, Leonberg, DE;
Bruno Michel, Zurich, CH;
Tim Niggemeier, Laatzen, DE;
Stephan Paredes, Zurich, CH;
Jochen Supper, Herrenberg, DE;
Harry Barowski, Boeblingen, DE;
Thomas Brunschwiler, Thalwil, CH;
Hubert Harrer, Schoenaich, DE;
Andreas Huber, Leonberg, DE;
Bruno Michel, Zurich, CH;
Tim Niggemeier, Laatzen, DE;
Stephan Paredes, Zurich, CH;
Jochen Supper, Herrenberg, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A mechanism is provided for integrated power delivery and distribution via a heat sink. The mechanism comprises a processor layer coupled to a signaling and input/output (I/O) layer via a first set of coupling devices and a heat sink coupled to the processor layer via a second set of coupling devices. In the mechanism, the heat sink comprises a plurality of grooves on one face, where each groove provides either a path for power or a path for ground to be delivered to the processor layer. In the mechanism, the heat sink is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism and the signaling and I/O layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.