Transistor structure with a sidewall-defined intrinsic base to extrinsic base link-up region and method of forming the structure

Abstract

Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance C, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rand a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Ccapacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer, the width of the conductive strap, the width of the dielectric spacer and the width of the emitter layer) to be selectively adjusted in order to optimize transistor performance.