The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 19, 2013
Filed:
Nov. 17, 2011
Ashok Mehta, Los Gatos, CA (US);
Stanley John, Fremont, CA (US);
Kai-yuan Ting, San Jose, CA (US);
Sandeep Kumar Goel, San Jose, CA (US);
Chao-yang Yeh, Luzhou, TW;
Ashok Mehta, Los Gatos, CA (US);
Stanley John, Fremont, CA (US);
Kai-Yuan Ting, San Jose, CA (US);
Sandeep Kumar Goel, San Jose, CA (US);
Chao-Yang Yeh, Luzhou, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A system includes an automated place and route tool to generate a layout of an integrated circuit (IC) die based on a gate level circuit description. A machine readable persistent storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second IC dies, respectively, and a second portion encoded with a second gate level description of the plurality of circuit patterns received from the tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented verification module is provided for comparing the first and second gate level descriptions and outputting an error report if the second gate level description has an error. The verification module outputs a verified second gate-level description of the first and second circuit patterns.