The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2013

Filed:

Nov. 16, 2010
Applicants:

Brian M. Czabaj, Essex Junction, VT (US);

James V. Hart, Iii, Washington, VT (US);

William J. Murphy, North Ferrisburgh, VT (US);

James S. Nakos, Essex Junction, VT (US);

Inventors:

Brian M. Czabaj, Essex Junction, VT (US);

James V. Hart, III, Washington, VT (US);

William J. Murphy, North Ferrisburgh, VT (US);

James S. Nakos, Essex Junction, VT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A ferro-electric random access memory (FRAM) chip, including a substrate; a first dielectric layer over the substrate; a gate over the first dielectric layer; a first aluminum oxide layer over the first dielectric layer and the gate; a second dielectric layer over the first aluminum oxide layer; a trench through the second dielectric layer and the first aluminum oxide layer to the gate; a hydrogen barrier liner over the second dielectric layer and lining the trench, and contacting the gate; and a silicon dioxide plug over the hydrogen barrier liner substantially filling the trench.


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