The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2013

Filed:

Jan. 23, 2007
Applicants:

Oscar Siguenza, San Jose, CA (US);

Duane Breid, Lakeville, MN (US);

Gene Sluss, Pleasanton, CA (US);

Deepak Sherlekar, Cupertino, CA (US);

Mike Colwell, Morgan Hill, CA (US);

Inventors:

Oscar Siguenza, San Jose, CA (US);

Duane Breid, Lakeville, MN (US);

Gene Sluss, Pleasanton, CA (US);

Deepak Sherlekar, Cupertino, CA (US);

Mike Colwell, Morgan Hill, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Various methods and apparatuses are described for a power distribution structure. In an embodiment, an integrated circuit contains power gating cells that each contain Metal Oxide Semiconductor (MOS) device switches located relative in the power distribution structure to power up and down a block of logic containing a plurality of individual cells using these MOS device switches. The MOS device switches can be tuned to requirements of a target block of logic in order to meet its optimal voltage drop requirements during its active operational state while minimizing leakage current in its off state.


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