The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 19, 2013
Filed:
Mar. 30, 2010
Chan-hong Chern, Palo Alto, CA (US);
Tzu Ching Chang, Dali, TW;
Min-shueh Yuan, Taipei, TW;
Yuwen Swei, Fremont, CA (US);
Chih-chang Lin, San Jose, CA (US);
Chiang Pu, San Jose, CA (US);
Ming-chieh Huang, San Jose, CA (US);
Kuoyuan Hsu, San Jose, CA (US);
Chan-Hong Chern, Palo Alto, CA (US);
Tzu Ching Chang, Dali, TW;
Min-Shueh Yuan, Taipei, TW;
Yuwen Swei, Fremont, CA (US);
Chih-Chang Lin, San Jose, CA (US);
Chiang Pu, San Jose, CA (US);
Ming-Chieh Huang, San Jose, CA (US);
Kuoyuan Hsu, San Jose, CA (US);
Abstract
A voltage regulator circuit with high accuracy and Power Supply Rejection Ratio (PSRR) is provided. In one embodiment, an op-amp with a voltage reference input to an inverting input has the first output connected to a PMOS transistor's gate. The PMOS transistor's source and drain are each connected to the power supply and the voltage regulator output. The voltage regulator output is connected to an NMOS transistor biased in saturation mode and a series of two resistors. The non-inverting input of the op-amp is connected in between the two resistors for the first feedback loop. The op-amp's second output is connected to the gate of the NMOS transistor through an AC-coupling capacitor for the second feedback loop. The op-amp's first output can be connected to the power supply voltage through a capacitor to further improve high frequency PSRR. In another embodiment, the role of PMOS and NMOS transistors is reversed.