The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2013

Filed:

Jun. 04, 2008
Applicants:

Will Wong, Daly City, CA (US);

Nghia Thuc Tu, San Jose, CA (US);

Jaime Bayan, Palo Alto, CA (US);

David Chin, Cupertino, CA (US);

Inventors:

Will Wong, Daly City, CA (US);

Nghia Thuc Tu, San Jose, CA (US);

Jaime Bayan, Palo Alto, CA (US);

David Chin, Cupertino, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/60 (2006.01); H01L 23/495 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. In one embodiment, a foil carrier structure is formed by ultrasonically bonding portions of a conductive foil to a metallic carrier. The bonded portions define panels in the foil carrier structure. In some embodiments, the foil carrier structure is cut to form multiple isolated panels that are sealed along their peripheries. Each isolated panel may be approximately the size of a conventional leadframe strip or panel. As a result, existing packaging equipment may be used to add dice, bonding wires and molding material to the panel. The ultrasonic welding helps prevent unwanted substances from penetrating the foil carrier structure during such processing steps. After the carrier portion of the molded foil carrier structure is removed, the structure is singulated into integrated circuit packages. Some embodiments relate to methods that utilize some or all of the aforementioned operations. Other embodiments relate to arrangements used in the above processes.


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