The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 05, 2013
Filed:
Jun. 06, 2011
Kang-wook Lee, Suwon-si, KR;
Gu-sung Kim, Seongnam-si, KR;
Dong-hyeon Jang, Suwon-si, KR;
Seung-duk Baek, Asan-si, KR;
Jae-sik Chung, Asan-si, KR;
Kang-Wook Lee, Suwon-si, KR;
Gu-Sung Kim, Seongnam-si, KR;
Dong-Hyeon Jang, Suwon-si, KR;
Seung-Duk Baek, Asan-si, KR;
Jae-Sik Chung, Asan-si, KR;
Samsung Electronics Co., Ltd., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;
Abstract
A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.